000101483 001__ 101483
000101483 005__ 20190416055704.0
000101483 022__ $$a0278-0070
000101483 02470 $$2DAR$$a10943
000101483 02470 $$2ISI$$a000247547200009
000101483 037__ $$aARTICLE
000101483 245__ $$aAn Application-Specific Design Methodology for On-chip Crossbar Generation
000101483 269__ $$a2007
000101483 260__ $$bInstitute of Electrical and Electronics Engineers$$c2007
000101483 336__ $$aJournal Articles
000101483 520__ $$aDesigning a power-efficient interconnection architec- ture for MultiProcessor Systems-on-Chips (MPSoCs) satisfying the application performance constraints is a nontrivial task. In order to meet the tight time-to-market constraints and to effec- tively handle the design complexity, it is essential to provide a computer-aided design tool support for automating this task. In this paper, we address the issue of “application-specific design of optimal crossbar architecture” satisfying the performance re- quirements of the application and optimal binding of the cores onto the crossbar resources. We present a simulation-based design approach that is based on the analysis of the actual traffic trace of the application, considering local variations in traffic rates, temporal overlap among traffic streams, and criticality of traffic streams. Our approach is physical design aware, where the wiring complexity of the crossbar architecture is also considered during the design process. This leads to detecting timing violations on the wires early in the design cycle and to having accurate estimates of the power consumption on the wires. We apply our methodology onto several MPSoC designs, and the synthesized crossbar plat- forms are validated for performance by cycle-accurate SystemC simulation of the designs. The crossbar matrix power consumption values are based on the synthesis of the register transfer level models of the designs, obtained using industry standard tools. The experimental case studies show large reduction in communication architecture power consumption (45.3% on average) and total wirelength (38% on average) for the MPSoC designs when com- pared with traditional design approaches. The synthesized cross- bar designs also lead to large reduction in transaction latencies (up to 7×) when compared with the existing design approaches.
000101483 6531_ $$aapplication specific
000101483 6531_ $$abus
000101483 6531_ $$acrossbar
000101483 6531_ $$afloorplan
000101483 6531_ $$anetworks-on-chips (NoCs)
000101483 6531_ $$asystemC
000101483 6531_ $$asystems-on-chips (SoCs)
000101483 6531_ $$atiming closure
000101483 700__ $$0242414$$g171633$$aMurali, Srinivasan
000101483 700__ $$0243773$$g171049$$aBenini, Luca
000101483 700__ $$aDe Micheli, Giovanni$$g167918$$0240269
000101483 773__ $$j26$$tIEEE Transactions on Computer Aided Design$$k7$$q1283-1296
000101483 8564_ $$uhttps://infoscience.epfl.ch/record/101483/files/Murali_04237239.pdf$$zn/a$$s836391$$yn/a
000101483 909C0 $$xU11140$$0252283$$pLSI1
000101483 909CO $$particle$$ooai:infoscience.tind.io:101483$$qGLOBAL_SET$$pSTI$$pIC
000101483 917Z8 $$x176271
000101483 917Z8 $$x176271
000101483 917Z8 $$x112915
000101483 937__ $$aEPFL-ARTICLE-101483
000101483 973__ $$rREVIEWED$$sPUBLISHED$$aEPFL
000101483 980__ $$aARTICLE