Nanostencil lithography is a flexible, rapid and resistless patterning method based on a high-resolution shadow mask. It allows for a wide choice of materials and surfaces to be structured and on the contrary to deep-ultraviolet (DUV), x-ray, electron beam, or ion beam exposure, mechanically fragile and chemically functionalized surfaces can be structured by this technique. One of the major limitations in nanostencil lithography is gap-induced pattern blurring. With the aim of integrating nanomechanical structures with CMOS circuits, we use nanostencil lithography as a clean, CMOS-compatible method to define the nanodevices using the stencil-deposited metal pattern as a mask for silicon reactive ion etching (RIE). Nanomechanical resonators are fabricated in a post-processing module after CMOS circuit fabrication. When the nanostencil membrane and the wafer are put in contact, a gap of more than 1 um exists between the layer to be structured and the stencil membrane. This gap genders a blurring of the resulting pattern by a dispersive effect. Correction of this loss of resolution with the goal of recovering nominal dimensions is the objective of the present study. We have focused on aluminium (Al) as deposition material because its RIE selectivity with respect to silicon is very high even for very thin Al layers. Experiments performed with a pre-defined gap between the stencil and the surface show a blurring effect due to the non-desired deposition of a thin metal layer extending from the abrupt flanks of the desired pattern. This thin layer is strong enough to resist a posterior RIE. We can avoid this effect by a controlled etching of a few nanometres of the deposited layer to uniformly decrease the layer thickness, thus eliminating the thin layer due to the blurring effect. We have been able to correct the blurring effect by developing a controlled dry Al etch process, using Quad Drytek equipment. Some initial unsuccessful tests of wet etching lead us to choose a dry etching process for reasons of uniformity, repeatability and controllability. Experiments have been performed on samples in which 70-nm-thick Al was deposited on a silicon wafer by nanostencil lithography. The technological process that has been developed consists on two main steps. First, specific conditions are determined to remove the thin native Al oxide layer, which is resistant to many chemical components: BCl3 50 sccm, 325 mT, 125 W, T=55 ºC. Then, chlorine chemistry is used to etch the pre-cleaned thin Al layer. Assuming a 25 nm Al etching as a minimal target, we use a mixture of Cl2 (as Al etchant): BCl3 (to reduce the etch rate by neutralizing H2O): N2 (for better uniformity and low etch rate) with a flow of 3/12/80 sccm respectively (rest of conditions: 325mT, 125W, average T=55ºC). The resulting etch rate is approximately 100 nm/min. Using this process, the pattern widening is corrected. The results obtained provide a clear remedy to overcome one of the major challenges in nanostencil-based surface patterning.