The aim of this paper is to present a novel approach to pattern silicon nanowires for advanced electronics applications. A simple non-lithographic process was successfully developed to define sub-40nm diameter silicon wires and to connect them to test pads. Silicon nanowires can be used as basic functional blocks for applications that require typically low power and high density integration (single electron devices , silicon nano-wires , MEMS-like nano-scale structures ). The process flow described here is CMOS-compatible, which is an attractive feature for the future hybridization of micro/nanoelectronics.