Silicon Nanowires Patterning by Sidewall and Nano-Oxidation Processing

The aim of this paper is to present a novel approach to pattern silicon nanowires for advanced electronics applications. A simple non-lithographic process was successfully developed to define sub-40nm diameter silicon wires and to connect them to test pads. Silicon nanowires can be used as basic functional blocks for applications that require typically low power and high density integration (single electron devices , silicon nano-wires , MEMS-like nano-scale structures ). The process flow described here is CMOS-compatible, which is an attractive feature for the future hybridization of micro/nanoelectronics.


Presented at:
Nanoelectronics Days 2005, Jülich, Germany, 9-11 Feb, 2005
Year:
2005
Laboratories:


Note: The status of this file is: EPFL only


 Record created 2007-02-08, last modified 2018-03-17

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