Diseño de redes en chip de propósito específico con información de rutado físico

The equivalent English title: "Design of Custom Networks-on-Chip with Physical Layout Information" Abstract translated into English: Due to the growing demand of communication between processors and memory devices in Systems-on-Chip (SoCs), recently the new NoC paradigm has been proposed for SoCs. In order to enable the use of NoCs as a feasible choice for the semiconductor industry, it is required to design custom NoCs for each type of application that we want to execute in the SoCs. In this paper we present a new methodology to design custom NoCs, which takes into consideration the physical layout information for the NoC links and the location in the system of the final SoC components when the topology definition process takes place. This enables detecting and eliminating possible time violations and correctly estimating the dissipated power in the interconnection system. This new design flow defines and instantiates in a completely automated way the synthesizable VHDL code for custom NoCs, including at the same different mechanisms to avoid the different types of routing deadlocks. Our results with several complex NoC-based systems prove that the final physical design of the NoC topology can be performed in less than 4 hours, instead of weeks that used to take. Also, this methodology achieves average gainsclose to 3x in power consumption and 2x in performance (enabling working frequencies of 900 MHz) with respect to the possible manual alternatives of mesh-based NoCs, Clos, etc.

Published in:
Proceedings of XVII Jornadas de Parelelismo, 597-602
Presented at:
XVII Jornadas de Parelelismo, Albacete, Spain, September 2006

 Record created 2007-02-06, last modified 2018-03-18

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