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  4. A low-power strategy for delta-sigma modulators
 
conference paper

A low-power strategy for delta-sigma modulators

Pesenti, S.
•
Clement, P.
•
Stefanovic, D.
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2007
Proceedings of the 14th International Conference on Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07.
Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07. 14th International Conference on

This paper presents a hybrid continuous-discrete-time Delta-Sigma modulator for portable communication systems following a low-power strategy. The proposed design methodology is extendable to different specifications. A multi-bit technique has been introduced in an efficient manner to optimize the power consumption, and an adaptive algorithm is used to allow for a 3-fold reduction in the number of comparators. Copyright © 2007 by Department of Microelectronics & Computer Science, Technical University of Lodz.

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Type
conference paper
DOI
10.1109/MIXDES.2007.4286151
Author(s)
Pesenti, S.
Clement, P.
Stefanovic, D.
Kayal, M.  
Date Issued

2007

Published in
Proceedings of the 14th International Conference on Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07.
ISBN of the book

83-922632-9-4

Start page

203

End page

208

Subjects

Auto-ranging algorithm

•

Delta-sigma modulator

•

Mismatch shaping encoder

•

Multibit

Note

Marvell Semiconductor, Route de Pallatex 17, CH-1163 Etoy, Switzerland Electronics Laboratory (LEG), Ecole Polytechnique Fédérale de Lausanne (EPFL), Station 11, CH-1015 Lausanne, Switzerland, Cited By (since 1996): 1, Export Date: 19 January 2010, Source: Scopus, Art. No.: 4286151, References: X. Lu, A novel signal-predicting multi-bit Delta-Sigma modulator, Proc. of the IEEE International Conference on Electronics Circuits and Systems, December 2004, pp. 105-108Zierhofer, C., Adaptive Sigma-Delta modulation with one-bit quantization (2000) IEEE Trans. on circuits and systems, pp. 408-415. , May; Dorrer, L., and al, A 3-mW74-dB SNR 2-MHz continuous-time Delta-Sigma ADC with a tracking ADC quantizer in 0.13-um CMOS (2002) IEEE J. of Solid-State Circuits, 37, pp. 1636-1644. , December; Fishov, A., Siracusa, E., Welz, J., Fogleman, E., Galton, I., Segmented mismatch-shaping D/A conversion (2002) Proc. Of the IEEE International Symposium on Circuits and Systems, 4, pp. 679-682. , May; Yan, S., Sanchez, S., A continuous-time Sigma-Delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth (2004) IEEE J. of Solid-State Circuits, 39, pp. 75-86. , January; Kappes, M., A 2.2-mW CMOS band-pass continuous-time multi-bit Delta-Sigma ADC with 68dB of dynamic range and 1MHz bandwidth for wireless applications (2003) IEEE J. of Solid-State Circuits, 38, pp. 1098-1104. , July; Schreier, R., Lloyd, J., Singer, L., Paterson, D., Timko, M., Hensley, M., Patterson, G., Zhou, J., A 10-300-MHz IF-digitizing IC with 90-105-dB dynamic range and 15-33-kHz bandwidth (2003) IEEE J. of Solid-State Circuits, 38, pp. 1098-1104. , December; Nguyen, K., Adams, R., Sweetland, K., Chen, H., A 106-dB SNR hybrid Over-sampling analog-todigital converter for digital audio (2005) IEEE J. of Solid-State Circuits, 40, pp. 2408-2414. , December; Morrow, P., Chamarro, M., Lyden, C., Ventura, P., Abo, A., Matamura, A., Keane, M., Ryan, I., A 0.18um 102dB-SNR mixed CT SC audio-band Delta-Sigma ADC (2005) IEEE International Solid-State Circuit Conference, pp. 178-179; Haykin, S., van Veen, B., (1999) Signals and Systems, , John Wiley & Sons Inc, New-York; Pastre, M., Kayal, M., (2006) Methodology for the digital calibration of analog circuits and systems with case studies, , Springer, Berlin; Kayal, M., Pastre, M., Automatic Calibration of Hall Sensor Microsystems Microelectronics Journal; Pastre, M., Kayal, M., Blanchard, H., Continuously gain-calibrated Hall sensor analog front-end for current measurement International Solid-State Circuits Conference (ISSCC), February 6 to 10-San Francisco-USA

URL

URL

http://tinyurl.com/2urvxyu
Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
GR-KA  
Event nameEvent placeEvent date
Mixed Design of Integrated Circuits and Systems, 2007. MIXDES '07. 14th International Conference on

Ciechocinek, Poland

June 21-23, 2007

Available on Infoscience
October 21, 2010
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/55946
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