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  4. Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications
 
conference paper

Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications

Casale Brunet, Simone  
•
Bezati, Endri  
•
Alberti, Claudio  
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2013
2013 Asilomar Conference on Signals, Systems and Computers
Asilomar Conference on Signals, Systems, and Computers
  • Details
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Type
conference paper
DOI
10.1109/ACSSC.2013.6810611
Author(s)
Casale Brunet, Simone  
Bezati, Endri  
Alberti, Claudio  
Mattavelli, Marco  
Amaldi, Edoardo
Janneck, Jorn
Date Issued

2013

Published in
2013 Asilomar Conference on Signals, Systems and Computers
Start page

1796

End page

1800

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
SCI-STI-MM  
Event nameEvent placeEvent date
Asilomar Conference on Signals, Systems, and Computers

Pacific Grove, CA, USA

3-6 November, 2013

Available on Infoscience
October 2, 2013
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/96046
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