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research article

Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces

Gharibdoust, Kiarash  
•
Tajalli, Seyed Armin  
•
Leblebici, Yusuf  
2015
IEEE Journal of Solid State Circuits (JSSC)

A 7.5 Gb/s mixed NRZ/multi-tone transceiver for multi-drop bus (MDB) memory interfaces is designed and fabricated in 40 nm CMOS technology. Reducing the complexity of the equalization circuitry on the receiver (RX) side, the proposed architecture achieves 1 pJ/bit link efficiency for a MDB channel with 45 dB loss at 2.5 GHz. The transmitted spectrum is composed of baseband (BB) and I /Q sub-bands with the ability to match the modulation frequency of the entire transceiver (TRX) with respect to the channel response over a +/- 25% range. A switched-capacitor-based mixer/filter is developed to efficiently down convert and equalize the I /Q sub-bands in the RX. The core size area is 85 x 60 um2 and 150 x 60 um2 for the TX and RX, respectively.

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Type
research article
DOI
10.1109/JSSC.2015.2483904
Web of Science ID

WOS:000366659700028

Author(s)
Gharibdoust, Kiarash  
•
Tajalli, Seyed Armin  
•
Leblebici, Yusuf  
Date Issued

2015

Publisher

Institute of Electrical and Electronics Engineers

Published in
IEEE Journal of Solid State Circuits (JSSC)
Volume

50

Issue

12

Start page

3133

End page

3144

Subjects

Decision-feedback equalizer (DFE)

•

multi-tone signaling

•

intersymbol interference (ISI)

URL

URL

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7302514
Peer reviewed

NON-REVIEWED

Written at

EPFL

EPFL units
LSM  
Available on Infoscience
September 17, 2015
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/117978
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