This paper presents a charge-sampling PLL (CSPLL), that demonstrates the best reported jitter-power FOM of -258.9 dB thanks to its high phase-detection gain and to the removal of the power-hungry buffer driving the phase detector. It also achieves -65 dBc of reference spur by both minimizing the modulated capacitance seen by the VCO tank and reducing the duty cycle of the sampling clock. Without requiring any RF dividers, a 50 mu W frequency tracking loop is also introduced to robustly lock the CSPLL to a 100MHz reference. Fabricated in 40-nm CMOS, the 0.13mm(2) CSPLL achieves an RMS jitter of 50 fsec at 11.4GHz while consuming 5mW.