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  4. Iterative Layering: Optimizing arithmetic circuits by structuring the information flow
 
conference paper

Iterative Layering: Optimizing arithmetic circuits by structuring the information flow

Verma, Ajay K.
•
Brisk, Philip
•
Ienne, Paolo  
2009
Proceedings of the International Conference on Computer Aided Design
International Conference on Computer Aided Design
  • Details
  • Metrics
Type
conference paper
DOI
10.1145/1687399.1687547
Author(s)
Verma, Ajay K.
Brisk, Philip
Ienne, Paolo  
Date Issued

2009

Published in
Proceedings of the International Conference on Computer Aided Design
ISBN of the book

978-1-60558-800-1

Start page

797

End page

804

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LAP  
Event nameEvent place
International Conference on Computer Aided Design

San Jose, California, USA

Available on Infoscience
August 31, 2015
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/117501
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