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  4. Enhanced Compressed Look-up-Table Based Real-Time Rectification Hardware
 
conference paper

Enhanced Compressed Look-up-Table Based Real-Time Rectification Hardware

Akin, Abdulkadir  
•
Gaemperle, Luis Manuel
•
Najibi, Halima
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Orailoglu, A
•
Ugurdag, Hf
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2015
Vlsi-Soc: At The Crossroads Of Emerging Trends
IFIP/IEEE WG 10.5 21st International Conference on Very Large Scale Integration (VLSI-SoC)

Real-time disparity estimation requires real-time rectification which involves solving the models of lens distortions, image translations and rotations. Low complexity look-up-table based rectification algorithms usually require an external memory to store large look-up-tables. In this chapter, we present an implementation of the look-up-table based approach which compresses the rectification information to fit the look-up-table into the on-chip memory of a Virtex-5 FPGA. First, a very low complexity compressed look-up-table based rectification algorithm (CLUTR) and its real-time hardware are presented. The implemented CLUTR hardware rectifies stereo images with moderate lens distortion and camera misalignment. Moreover, an enhanced version of the compressed look-up-table based rectification algorithm (E-CLUTR) and its novel real-time hardware are presented. E-CLUTR solves more extreme camera alignment and distortion issues than CLUTR while maintaining the low complexity architecture.

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Type
conference paper
DOI
10.1007/978-3-319-23799-2_11
Web of Science ID

WOS:000364780900011

Author(s)
Akin, Abdulkadir  
Gaemperle, Luis Manuel
Najibi, Halima
Schmid, Alexandre  
Leblebici, Yusuf  
Editors
Orailoglu, A
•
Ugurdag, Hf
•
Silveira, Lm
•
Margala, M
•
Reis, R
Date Issued

2015

Publisher

Springer-Verlag Berlin

Publisher place

Berlin

Published in
Vlsi-Soc: At The Crossroads Of Emerging Trends
ISBN of the book

978-3-319-23799-2

Total of pages

22

Series title/Series vol.

IFIP Advances in Information and Communication Technology

Volume

461

Start page

227

End page

248

Subjects

Stereo matching

•

Image rectification

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Compression

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Real-time

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Hardware implementation

•

FPGA

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
IEL  
Event nameEvent placeEvent date
IFIP/IEEE WG 10.5 21st International Conference on Very Large Scale Integration (VLSI-SoC)

Ozyegin Univ, Istanbul, TURKEY

OCT 06-09, 2013

Available on Infoscience
February 16, 2016
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/123711
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