A Power-Efficient LVDS Driver Circuit in 0.18-μm CMOS Technology
This article presents a power-efficient and low-voltage CMOS output driver circuit based on low-voltage differential signaling (LVDS) standard. To reduce the ringing at the output of the proposed driver circuit and simultaneously keep the power consumption low, a new technique has been applied to control the output voltage slew. A pre-driver circuit is also utilized to have a very low total equivalent input capacitance of 50 fF. Designed in 0.18 μm CMOS technology, the entire output driver circuit including the input pre-driver, draws only 5.6 mArms while the output voltage swing is VOD = 400 mV and the other specs are compliant with the LVDS requirements.
WOS:000255548900037
2007
Piscataway, NJ, USA
978-1-4244-1000-2
145
148
REVIEWED
EPFL
Event name | Event place | Event date |
Bordeaux | July 2-5 | |