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  4. Modeling and Design Space of Junctionless Symmetric DG MOSFETs With Long Channel
 
research article

Modeling and Design Space of Junctionless Symmetric DG MOSFETs With Long Channel

Jazaeri, Farzan  
•
Barbut, Lucian  
•
Sallese, Jean-Michel  
2013
IEEE Transactions on Electron Devices

We investigate the technological con-strains and design limitations of ultrathin body junctionless dou- ble gate MOSFET (JL DG MOSFET). Relationships between the silicon thickness and the doping concentration compatible with design requirements in terms of OFF-state-current and voltages are obtained and validated with TCAD simulations. This set of analytical expressions can be used as a guideline for technology optimization of JL DG MOSFETS.

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Type
research article
DOI
10.1109/TED.2013.2261073
Web of Science ID

WOS:000320870000005

Author(s)
Jazaeri, Farzan  
Barbut, Lucian  
Sallese, Jean-Michel  
Date Issued

2013

Publisher

Ieee-Inst Electrical Electronics Engineers Inc

Published in
IEEE Transactions on Electron Devices
Volume

60

Issue

7

Start page

2120

End page

2127

Subjects

Compact model

•

double gate MOSFETS

•

junctionless

•

nanowire

•

OFF-state-current

•

subthreshold

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

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EDLAB  
Available on Infoscience
August 7, 2013
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/93957
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