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conference paper

Integrated ESOP Refactoring for Industrial Designs

Haaswijk, Winston  
•
Amaru, Luca G.  
•
Vuillod, Patrick
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January 1, 2018
2018 25Th Ieee International Conference On Electronics, Circuits And Systems (Icecs)
25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

We present a multi-level logic refactoring algorithm based on exclusive sum-of-product (ESOP) expressions. ESOP expressions are two-level logic representation forms, similar to sum of -product (SOP) expressions. However, ESOPs use EXOR instead of OR operators. It has been shown that this allows ESOPs to be exponentially more compact than SOP expressions for important classes of functions. Our algorithm is based on a combination of ESOP collapsing, minimization, and refactoring. In EXOR-heavy logic, such as arithmetic units, it unlocks optimizations that may be outside the reach of SOP based methods. We show that our method is able to significantly improve upon logic optimization results, as compared to a similar SOP based flow. On a set of EXOR-heavy benchmarks, we reduce logic levels by up to 833% in the best case, and by 44.6% on average. Further, we are able to reduce logic network size by 21.4% on average. We have integrated our method into a commercial synthesis flow. On a set of 46 industrial benchmarks, the optimizations introduced by our algorithm improve design results after physical synthesis.

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Type
conference paper
DOI
10.1109/ICECS.2018.8617963
Web of Science ID

WOS:000458965100092

Author(s)
Haaswijk, Winston  
Amaru, Luca G.  
Vuillod, Patrick
Luo, Jiong
Soeken, Mathias  
De Micheli, Giovanni  
Date Issued

2018-01-01

Publisher

IEEE

Publisher place

New York

Published in
2018 25Th Ieee International Conference On Electronics, Circuits And Systems (Icecs)
ISBN of the book

978-1-5386-9562-3

Series title/Series vol.

IEEE International Conference on Electronics Circuits and Systems

Start page

369

End page

372

Subjects

Engineering, Electrical & Electronic

•

Engineering

•

of-products expressions

•

multiple-valued-input

•

minimization

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LSI1  
Event nameEvent placeEvent date
25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

Bordeaux, FRANCE

Dec 09-12, 2018

Available on Infoscience
June 18, 2019
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/157060
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