This brief proposes a low-voltage, high-precision, and high-dynamic-range current-mode analog winner-take-all (WTA) circuit. The proposed structure employs a new high-gain stage as a feedback network between the input node of each cell and the common node of the circuit to reduce the sensitivity of the output current to the loser signals, especially when they are close to the winner. In addition, another network is employed that senses the amount of the output/winner current and adjusts the bias current of the gain stages. This ensures that the drain-source voltage of the input transistor in the winner cell matches the behavior of the output transistor's drain-source voltage, enhancing the accuracy as well as the input dynamic range (DR) of the structure. Moreover, since the circuit works properly with a minimum supply voltage of only VGS + Veff, it is a promising candidate for applications in emerging technologies with low supply voltage requirements. Based on the proposed structure, a three-input WTA circuit is designed and fabricated in a 0.18-μm CMOS technology. According to the measurement results, the proposed circuit exhibits a maximum error of 1.5% for the input signal range of 60μ A when the input frequency is 100 kHz. The silicon area occupied by the circuit is 33μm × 65μm.