This paper presents the design and implementation of a multiplying delay-locked loop (MDLL) in 40 nm bulk CMOS process, which can be used as clock and data recovery (CDR) unit in source-synchronous wire-line communications. The MDLL multiplies the reference frequency and delivers differential inphase (I) and quadrature (Q) clocks by generating 8 equally spaced clock phases and combining these phases appropriately. A technique for reducing deterministic jitter (DJ) in MDLL is proposed. The prototype dissipates 1.1-1.8 mW over output frequency range of 2.6-6.4 GHz, while the RMS jitter and I/Q mismatch remain below 3ps rms and 5 degree, respectively, over the entire range. The core size occupies 60x40 um2 silicon area.