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  4. Scaled-Footprint Ultra-Low Power Cryogenic InGaAs/InP HEMTs with Record-High Combination of Low-Noise and High-Frequency Performance
 
conference paper

Scaled-Footprint Ultra-Low Power Cryogenic InGaAs/InP HEMTs with Record-High Combination of Low-Noise and High-Frequency Performance

Ferraris, Alberto  
•
Cha, Eunjung
•
Olziersky, Antonis
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2025
2025 Symposium on VLSI Technology and Circuits [Digest of Technical Papers]
2025 IEEE Symposium on VLSI Technology and Circuits: “Cultivating the VLSI Garden: From Seeds of Innovation to Thriving Growth“

In this work we demonstrate cryogenic InxGa1-xAs/InP HEMTs with highly scaled gate footprints, down to 380 × 40 nm2 for a single gate finger, and investigate the impact of footprint scaling on device performance. The 80% In channel devices show fT=622 GHz and fMAX=733 GHz together with a noise indication factor √ID/gm=0.17 √V·mm/S at 4 K, which is a record-high combination of high-frequency and low-noise performance. The performance is enabled by heterostructure engineering, resulting in ultra-low RON=250 Ω·μ m together with a minimum subthreshold swing SS < 10 mV/decade. These results show that cryogenic III-V HEMT technology can provide excellent performance at scaled footprints for readout in future high-density quantum systems.

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Type
conference paper
DOI
10.23919/VLSITechnologyandCir65189.2025.11075154
Scopus ID

2-s2.0-105012169871

Author(s)
Ferraris, Alberto  

IBM Research - Zurich

Cha, Eunjung

IBM Research - Zurich

Olziersky, Antonis

IBM Research - Zurich

Sousa, Marilyne

IBM Research - Zurich

Han, Hung-Chi  

EPFL

Charbon, Edoardo  

EPFL

Moselund, Kirsten Emilie  

EPFL

Zota, Cezar

IBM Research - Zurich

Date Issued

2025

Publisher

Institute of Electrical and Electronics Engineers Inc.

Published in
2025 Symposium on VLSI Technology and Circuits [Digest of Technical Papers]
DOI of the book
https://doi.org/10.23919/VLSITechnologyandCir65189.2025
ISBN of the book

9784863488151

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
INPHO  
AQUA  
Event nameEvent acronymEvent placeEvent date
2025 IEEE Symposium on VLSI Technology and Circuits: “Cultivating the VLSI Garden: From Seeds of Innovation to Thriving Growth“

2025 VLSI

Kyoto, Japan

2025-06-08 - 2025-06-12

FunderFunding(s)Grant NumberGrant URL

NCCR SPIN

SNSF

51NF40-180604,IZKSZ2-218591

Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/252943
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