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  4. Design of Completion Detection Circuits for Self-timed Systems Operating in Subthreshold Regime
 
conference paper

Design of Completion Detection Circuits for Self-timed Systems Operating in Subthreshold Regime

Akgun, Omer Can  
•
Leblebici, Yusuf  
•
Vittoz, Eric A.  
2007
Proceedings of 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

In this paper implementation of a novel completion detection method for self-timed, asynchronous subthreshold circuits is presented. By employing the self-timed operation principle, substantial speed gains in the operation of the asynchronous pipelines can be realized. The completion detection system is very simple, consisting of a sensor transistor, a very basic AC-coupled amplifier and a monostable multivibrator. The proposed method can be easily integrated into the CMOS design flow. The advantages of the proposed completion detection system is shown through simulations on an 8-bit ripple carry adder in a standard 0.18µm CMOS process operating at 400mV supply voltage.

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Type
conference paper
DOI
10.1109/RME.2007.4401857
Web of Science ID

WOS:000255548900061

Author(s)
Akgun, Omer Can  
•
Leblebici, Yusuf  
•
Vittoz, Eric A.  
Date Issued

2007

Published in
Proceedings of 3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
Start page

241

End page

244

Subjects

Completion detection

•

self-timed

•

asynchronous

•

subthreshold

Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LSM  
Event nameEvent placeEvent date
3rd IEEE Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

Bordeaux

July 2 - 5

Available on Infoscience
June 25, 2007
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/9312
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