research article
An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks
We propose an ultra-low-power (ULP) image signal processor (ISP) that performs on-the-fly in-processing frame compression/decompression and hierarchical event recognition to exploit the temporal and spatial sparsity in an image sequence. This approach reduces energy consumption spent processing and transmitting unimportant image data to achieve a 16 × imaging system energy gain in an intruder detection scenario. The ISP was fabricated in 40-nm CMOS and consumes only 170 μW at 5 frames/s for neural network-based intruder detection and 192 × compressed image recording.
Type
research article
Author(s)
An, Hyochan
Schiferl, Sam
Venkatesan, Siddharth
Wesley, Tim
Zhang, Qirui
Wang, Jingcheng
Liu, Shiyu
Liu, Bowen
Li, Ziyun
Date Issued
2020
Publisher
Published in
Volume
56
Issue
4
Start page
1071
End page
1081
Editorial or Peer reviewed
REVIEWED
Written at
OTHER
EPFL units
Available on Infoscience
April 1, 2022
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