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  4. An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks
 
research article

An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks

An, Hyochan
•
Schiferl, Sam
•
Venkatesan, Siddharth
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2020
IEEE Journal of Solid-State Circuits

We propose an ultra-low-power (ULP) image signal processor (ISP) that performs on-the-fly in-processing frame compression/decompression and hierarchical event recognition to exploit the temporal and spatial sparsity in an image sequence. This approach reduces energy consumption spent processing and transmitting unimportant image data to achieve a 16 × imaging system energy gain in an intruder detection scenario. The ISP was fabricated in 40-nm CMOS and consumes only 170 μW at 5 frames/s for neural network-based intruder detection and 192 × compressed image recording.

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Type
research article
DOI
10.1109/JSSC.2020.3041858
Author(s)
An, Hyochan
Schiferl, Sam
Venkatesan, Siddharth
Wesley, Tim
Zhang, Qirui
Wang, Jingcheng
Choo, Kyojin D.  
Liu, Shiyu
Liu, Bowen
Li, Ziyun
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Date Issued

2020

Publisher

IEEE

Published in
IEEE Journal of Solid-State Circuits
Volume

56

Issue

4

Start page

1071

End page

1081

Subjects

Deep neural network (DNN)

•

energy-efficient processor

•

event recognition

•

image compression

•

image signal processor (ISP)

Editorial or Peer reviewed

REVIEWED

Written at

OTHER

EPFL units
MSIC-LAB  
Available on Infoscience
April 1, 2022
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/186843
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