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conference paper

Towards 6G: Configurable High-Throughput Decoder Implementation for SC-LDPC Codes

Ren, Yuqing  
•
Shen, Yifei  
•
Song, W.  
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October 27, 2024
Conference Record of The Fifty-Eighth Asilomar Conference on Signals, Systems & Computers
2024 58th Asilomar Conference on Signals, Systems, and Computers

Spatially-coupled low-density parity-check (SC-LDPC) codes are considered an important candidate for the upcoming 6G standardization, owing to their superior error-correction capability and practical decoding complexity. However, current high-throughput SC-LDPC decoders rely on unrolled architectures tailored to a certain code and thus lack the necessary rate compatibility for wireless communications. In this paper, we present a fully reconfigurable decoder architecture for SC-LDPC codes. This hardware architecture can decode virtually any SC-LDPC code that fits in the allocated memories. Based on simplified routing networks, our SC-LDPC decoder can deliver extensive code length and code rate support and achieve high throughput to satisfy the requirements of 6G.

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Type
conference paper
DOI
10.1109/ieeeconf60004.2024.10942947
Author(s)
Ren, Yuqing  
•
Shen, Yifei  
•
Song, W.  
•
Balatsoukas-Stimming, Alexios
•
Boutillon, Emmanuel
•
Burg, Andreas  
Date Issued

2024-10-27

Publisher

IEEE

Published in
Conference Record of The Fifty-Eighth Asilomar Conference on Signals, Systems & Computers
DOI of the book
https://doi.org/10.1109/IEEECONF60004.2024
ISBN of the book

979-8-3503-5405-8

Start page

980

End page

984

Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
TCL  
Event nameEvent acronymEvent placeEvent date
2024 58th Asilomar Conference on Signals, Systems, and Computers

Pacific Grove, CA, USA

2024-10-27 - 2024-10-30

Available on Infoscience
April 15, 2025
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/249264
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