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  4. Challenges in Automatic Optimization of Arithmetic Circuits
 
conference paper

Challenges in Automatic Optimization of Arithmetic Circuits

Verma, Ajay K.
•
Brisk, Philip
•
Ienne, Paolo  
2009
Arith: 2009 19Th Ieee International Symposium On Computer Arithmetic
19th IEEE Symposium on Computer Arithmetic (ARITH 2009)

Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open and largely unsolved problem, especially for arithmetic circuits. In many cases, the outcome of even the most advanced synthesis techniques is highly dependent on the input description of the circuit, and the optimizations themselves barely modify the architecture of the circuit itself. Once the input description is converted to an appropriate architecture, logic synthesis performs local optimizations quite effectively; however, finding the best architecture up front is a nontrivial problem. This paper reviews recent results in arithmetic logic synthesis that the authors have published in recent years. Progress has clearly been made, but much further work is still needed to narrow the gap between the effectiveness of logic synthesis techniques for arithmetic and control-oriented circuits.

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Type
conference paper
DOI
10.1109/ARITH.2009.39
Web of Science ID

WOS:000272786700024

Author(s)
Verma, Ajay K.
Brisk, Philip
Ienne, Paolo  
Date Issued

2009

Publisher

Ieee Computer Soc Press, Customer Service Center, Po Box 3014, 10662 Los Vaqueros Circle, Los Alamitos, Ca 90720-1264 Usa

Published in
Arith: 2009 19Th Ieee International Symposium On Computer Arithmetic
Start page

213

End page

218

Subjects

Parallel Multipliers

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LAP  
Event nameEvent placeEvent date
19th IEEE Symposium on Computer Arithmetic (ARITH 2009)

Portland, OR

Jun 08-10, 2009

Available on Infoscience
November 30, 2010
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/59551
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