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  4. VLSI implementation of a high-speed iterative sorted MMSE QR decomposition
 
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conference paper

VLSI implementation of a high-speed iterative sorted MMSE QR decomposition

Luethi, P.
•
Burg, A.  
•
Haene, S.
Show more
2007
2007 Ieee International Symposium On Circuits And Systems
IEEE International Symposium on Circuits and Systems

The QR decomposition is an important, but often underestimated prerequisite for pseudo- or non-linear detection methods such as successive interference cancellation or sphere decoding for multiple-input multiple-output (MIMO) systems. The ability of concurrent iterative sorting during the QR decomposition introduces a moderate overall latency, but provides the base for an improved layered stream decoding. This paper describes the architecture and results of the first VLSI implementation of an iterative sorted QR decomposition preprocessor for MIMO receivers. The presented architecture performs MIMO channel preprocessing using Givens rotations in order to compute the minimum mean squared error QR decomposition.

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Type
conference paper
DOI
10.1109/ISCAS.2007.378495
Web of Science ID

WOS:000251608401177

Author(s)
Luethi, P.
•
Burg, A.  
•
Haene, S.
•
Perels, D.
•
Felber, N.
•
Fichtner, W.
Date Issued

2007

Publisher

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa

Journal
2007 Ieee International Symposium On Circuits And Systems
ISBN of the book

978-1-4244-0920-4

Start page

1421

End page

1424

Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
TCL  
Event nameEvent placeEvent date
IEEE International Symposium on Circuits and Systems

New Orleans, LA

May 27-30, 2007

Available on Infoscience
June 6, 2011
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/68384
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