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research article

Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation

Marukame, Takao
•
Ueyoshi, Kodai
•
Asai, Tetsuya
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2017
IEEE Transactions on Circuits and Systems II: Express Briefs

Remarkable hardware robustness of deep learning (DL) is revealed by error injection analyses performed using a custom hardware model implementing parallelized restricted Boltzmann machines (RBMs). RBMs in deep belief networks demonstrate robustness against memory errors during and after learning. Fine-tuning significantly affects the recovery of accuracy for static errors injected to the structural data of RBMs. The memory error tolerance is observable using our hardware networks with fine-graded memory distribution, resulting in reliable DL hardware with low-voltage driven memory suitable to low-power applications.

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Type
research article
DOI
10.1109/Tcsii.2016.2585675
Web of Science ID

WOS:000400566100022

Author(s)
Marukame, Takao
Ueyoshi, Kodai
Asai, Tetsuya
Motomura, Masato
Schmid, Alexandre
Suzuki, Masamichi
Higashi, Yusuke
Mitani, Yuichiro
Date Issued

2017

Publisher

Ieee-Inst Electrical Electronics Engineers Inc

Published in
IEEE Transactions on Circuits and Systems II: Express Briefs
Volume

64

Issue

4

Start page

462

End page

466

Subjects

Deep learning (DL)

•

fault tolerance

•

low power

•

restricted Boltzmann machines (RBMs)

•

static random access memory (SRAM)

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
IEL  
Available on Infoscience
May 30, 2017
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/137980
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