conference paper
Analysis of CMS noise reduction for 65 nm CIS
May 28, 2017
2017 IEEE International Symposium on Circuits and Systems (ISCAS)
This work explores the combination of a downscaled technology with in-pixel source-follower (SF) optimization, a high column-level gain and an analog implementation of Correlated-Multiple-Sampling (CMS) for noise reduction of CIS readout chains. Transient noise simulations show that in the optimal condition of a pMOS SF, a column-level gain equal to 64 and a CMS of order 8, the noise can be reduced to the extremely low value of 0.20e-rms, with a readout time of 43 μs, demonstrating the possibility of true photoelectron counting for this standard 65 nm process.
Type
conference paper
Author(s)
Date Issued
2017-05-28
Published in
2017 IEEE International Symposium on Circuits and Systems (ISCAS)
Editorial or Peer reviewed
REVIEWED
Written at
EPFL
EPFL units
| Event name | Event place | Event date |
Baltimore, MD, USA | 28-31 May 2017 | |
Available on Infoscience
February 2, 2018
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