This paper presents a low power successive approximation register (SAR) ADC and its front-end automatic gain control (AGC) amplifier designed in 65nm CMOS technology. Digitally controlled variable gain amplifier (VGA) in AGC loop is used to maximize the dynamic range. By adding the VGA front-end before the ADC, the dynamic range is improved by 20 dB and 48 dB SNDR is achieved for -40 dBV input signal. The VGA front-end also converts the single ended input signal into differential to be used in a differential SAR ADC design. VGA area is kept smaller by employing floating tunable high-value active resistors instead of passive resistors. The designed 10-bit SAR ADC can operate at a very wide range of sampling rates between 1 kS/s and 85 MS/s by changing the sampling duration from 1 to 3 clock cycles at the higher end of this sampling rate range. By using the programmable sampling duration technique, the maximum sampling rate of the ADC without compromising the SNDR performance is increased from 45 MS/s to 85 MS/s and around 10 dB improvement in SNDR is achieved at 85 MS/s sampling rate. The proposed analog front-end design including SAR ADC and AGC amplifier consumes 200 uW at 83.3 kS/s sampling rate and occupies 0.29mm(2) area.