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  4. Fault-Tolerant Logic Gates with Neuromorphic CMOS Circuits
 
conference paper

Fault-Tolerant Logic Gates with Neuromorphic CMOS Circuits

Joye, Neil  
•
Schmid, Alexandre  
•
Asai, Tetsuya
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2005
Proceedings of the Ninth International Conference on Cognitive and Neural Systems (ICCNS '05)
Ninth International Conference on Cognitive and Neural Systems
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Type
conference paper
Author(s)
Joye, Neil  
Schmid, Alexandre  
Asai, Tetsuya
Leblebici, Yusuf  
Date Issued

2005

Published in
Proceedings of the Ninth International Conference on Cognitive and Neural Systems (ICCNS '05)
Volume

II

Issue

29

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LSM  
Event nameEvent placeEvent date
Ninth International Conference on Cognitive and Neural Systems

Boston, Massachusetts, USA

May 18-21

Available on Infoscience
December 6, 2005
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/220815
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