Unleashing Parallelism in Elastic Circuits with Faster Token Delivery
High-level synthesis (HLS) is the process of automatically generating circuits out of high-level language descriptions. Previous research has shown that dynamically scheduled HLS through elastic circuit generation is successful at exploiting parallelism in some important use-cases. Nevertheless, the literal conversion of a standard compiler's control-data flow graph into elastic circuits often produces circuits with notable resource demands and inferior performance. In this work, we present a methodology for generating more area- and timing-efficient elastic circuits. We show that our strategy results in significant area and timing improvements compared to previous circuit generation strategies.
WOS:000975890500034
2022-01-01
Los Alamitos
978-1-6654-7390-3
International Conference on Field Programmable Logic and Applications
253
261
REVIEWED
EPFL
Event name | Event place | Event date |
Belfast, NORTH IRELAND | Aug 29-Sep 02, 2022 | |