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  4. Spatial: A Language and Compiler for Application Accelerators
 
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conference paper

Spatial: A Language and Compiler for Application Accelerators

Koeplinger, David
•
Feldman, Matthew
•
Prabhakar, Raghu
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April 1, 2018
ACM Sigplan Notices
39th ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)

Industry is increasingly turning to reconfigurable architectures like FPGAs and CGRAs for improved performance and energy efficiency. Unfortunately, adoption of these architectures has been limited by their programming models. HDLs lack abstractions for productivity and are difficult to target from higher level languages. HLS tools are more productive, but offer an ad-hoc mix of software and hardware abstractions which make performance optimizations difficult.

In this work, we describe a new domain-specific language and compiler called Spatial for higher level descriptions of application accelerators. We describe Spatial's hardware-centric abstractions for both programmer productivity and design performance, and summarize the compiler passes required to support these abstractions, including pipeline scheduling, automatic memory banking, and automated design tuning driven by active machine learning. We demonstrate the language's ability to target FPGAs and CGRAs from common source code. We show that applications written in Spatial are, on average, 42% shorter and achieve a mean speedup of 2.9x over SDAccel HLS when targeting a Xilinx UltraScale+ VU9P FPGA on an Amazon EC2 F1 instance.

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Type
conference paper
DOI
10.1145/3192366.3192379
Web of Science ID

WOS:000452469600021

Author(s)
Koeplinger, David
•
Feldman, Matthew
•
Prabhakar, Raghu
•
Zhang, Yaqi
•
Hadjis, Stefan
•
Fiszel, Ruben
•
Zhao, Tian
•
Nardi, Luigi
•
Pedram, Ardavan
•
Kozyrakis, Christos  
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Date Issued

2018-04-01

Publisher

ASSOC COMPUTING MACHINERY

Publisher place

New York

Published in
ACM Sigplan Notices
Volume

53

Issue

4

Start page

296

End page

311

Subjects

Computer Science, Software Engineering

•

Computer Science

•

domain-specific languages

•

compilers

•

hardware accelerators

•

high-level synthesis

•

reconfigurable architectures

•

fpgas

•

cgras

Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
IINFCOM  
Event nameEvent placeEvent date
39th ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)

Philadelphia, PA

Jun 18-22, 2018

Available on Infoscience
December 21, 2018
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/153129
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