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conference paper

A model for robust electrostatic design of nanowire FETs with arbitrary polygonal cross sections

De Michielis, L.  
•
Selmi, L.
•
Lonescu, A. M.
2009
ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference

In this work a quasi-analytical physical model for the accurate prediction of the potential of GAA nanowire transistors with an arbitrary regular polygon as a cross section is developed. Two case studies concerning triangular and square cross-sections are particularly investigated and analyzed. The model is then extended to the transport direction; general expressions for the natural length are derived and validated by means of two- and three-dimensional numerical device simulations. Basic design guidelines, using an original analytical expression of the natural length, for robust electrostatic design are proposed, to predict the minimum technological gate length able to assure immunity to the SeEs. ©2009 IEEE.

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Type
conference paper
DOI
10.1109/ESSDERC.2009.5331322
Author(s)
De Michielis, L.  
•
Selmi, L.
•
Lonescu, A. M.
Date Issued

2009

Journal
ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference
Start page

472

End page

475

Peer reviewed

NON-REVIEWED

Written at

EPFL

EPFL units
NANOLAB  
Available on Infoscience
November 8, 2010
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/57226
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