For more than four decades, <em>Complementary Metal-Oxide- Semiconductor</em> (CMOS) <i>Field Effect Transistors</i> (FETs) have been the baseline technology for implementing digital computation systems. CMOS transistors natively implement <em>Not-AND</em> (NAND)- and <em>Not- OR</em> (NOR)-based logic operators. Nowadays, we observe a trend towards devices with an increased set of logic capabilities, i.e., with the ability to realize in a compact way specific logic operators as compared to the standard CMOS. In particular, controllable-polarity devices enable a native and compact realization of <em>eXclusive-OR</em> (XOR)- and <em>MAJority</em> (MAJ)- logic functions, and open a large panel of opportunities for future high-performance computing systems. However, main current logic synthesis tools exploit algorithms using NAND/NOR representations that are not able to fully exploit the capabilities of novel XOR- and MAJ-oriented technologies. In this paper, we review some recent work that aims at providing novel logic synthesis techniques that natively assess the logic capabilities of XOR- and MAJ-operators.