There are mainly three well-known techniques to acquire a GNSS signal. The first, called Serial Search Acquisition, consist in correlating the Pseudo-Random Noise (PRN) codes for all the codes phases and all the frequency bins. The two others make use of the Fourier Transform in order to parallelize the search, either in the frequency space (Parallel Frequency Space Search Acquisition) or in the code space (Parallel Code Space Search Acquisition). The last two methods make parallelization inherently, but it is also possible to make parallelization with the first method by using multiple correlators testing several code phases at the same time. This paper provides an assessment of the resources required for each method, in terms of circuit, memory and processing power for the case of a hardware based receiver implemented into a FPGA. The associated performances are also provided and compared. The study is based on GPS L1 signal, but the methodology can easily be applied to others GNSS signals.