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conference paper

Hardware Decoders for Polar Codes: An Overview

Giard, Pascal  
•
Sarkis, Gabi
•
Balatsoukas-Stinning, Alexios
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2016
2016 Ieee International Symposium On Circuits And Systems (Iscas)
IEEE International Symposium on Circuits and Systems (ISCAS)

Polar codes are an exciting new class of error correcting codes that achieve the symmetric capacity of memoryless channels. Many decoding algorithms were developed and implemented, addressing various application requirements: from error-correction performance rivaling that of LDPC codes to very high throughput or low-complexity decoders. In this work, we review the state of the art in polar decoders implementing the successive-cancellation, belief propagation, and list decoding algorithms, illustrating their advantages.

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Type
conference paper
DOI
10.1109/ISCAS.2016.7527192
Web of Science ID

WOS:000390094700038

Author(s)
Giard, Pascal  
•
Sarkis, Gabi
•
Balatsoukas-Stinning, Alexios
•
Fan, Youzhe
•
Tsui, Chi-Ying
•
Burg, Andreas  
•
Thibeault, Claude
•
Gross, Warren J.
Date Issued

2016

Publisher

Ieee

Publisher place

New York

Published in
2016 Ieee International Symposium On Circuits And Systems (Iscas)
ISBN of the book

978-1-4799-5341-7

Total of pages

4

Series title/Series vol.

IEEE International Symposium on Circuits and Systems

Start page

149

End page

152

Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
TCL  
Event nameEvent placeEvent date
IEEE International Symposium on Circuits and Systems (ISCAS)

Montreal, CANADA

MAY 22-25, 2016

Available on Infoscience
January 24, 2017
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/133895
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