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conference paper

Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier

De Michielis, L.  
•
Lattanzio, L.  
•
Palestri, P.
Show more
2011
69th Device Research Conference
2011 69th Annual Device Research Conference (DRC)

The Tunnel-FET (TFET) device is a gated reverse biased p-i-n junction whose working principle is based on the quantum mechanical Band-to-Band Tunneling (B2BT) mechanism [1]. The OFF-ON transition can be much more abrupt than for conventional MOSFETs, thus allowing a reduction of the supply voltage and power consumption in logic applications [2]. Several TFETs with point Subthreshold Swing (SS) lower than 60mV/dec have been experimentally demonstrated with different architectures as conventional single gate Silicon-on-Insulator (SOI), Double Gate (DG) and Gate-All-Around (GAA) [3,4]. Unfortunately in all cases a relatively large average SS and a poor on-current have been observed. © 2011 IEEE.

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Type
conference paper
DOI
10.1109/DRC.2011.5994440
Author(s)
De Michielis, L.  
•
Lattanzio, L.  
•
Palestri, P.
•
Selmi, L.
•
Ionescu, A. M.  
Date Issued

2011

Publisher

IEEE

Published in
69th Device Research Conference
Start page

111

End page

112

Subjects

FP7 STEEPER

•

Tunnel FET

•

TFET

Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
NANOLAB  
Event nameEvent placeEvent date
2011 69th Annual Device Research Conference (DRC)

Santa Barbara, CA, USA

June 20-22, 2011

Available on Infoscience
January 19, 2012
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/76784
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