conference paper
Single-photon Avalanche Diodes in sub-100nm Standard CMOS Technologies
2011
Proc. Intl. Image Sensor Workshop (IISW)
Single-photon avalanche diodes (SPADs) are evaluated in two sub-100nm CMOS technologies. Several geometries are implemented, whereas premature edge breakdown (PEB) prevention is achieved with n-well rings. The octagonal SPADs are implemented in 90nm and 65nm standard CMOS technologies. Full characterization of SPAD performance is carried out as a function of bias and temperature. To the best of our knowledge, this is the first report of SPAD in any 65nm CMOS technology.
Type
conference paper
Author(s)
Date Issued
2011
Published in
Proc. Intl. Image Sensor Workshop (IISW)
Editorial or Peer reviewed
REVIEWED
Written at
OTHER
EPFL units
| Event name | Event date |
June, 2011 | |
Available on Infoscience
June 12, 2012
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