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  4. Towards generic low-power area-efficient standard cell based memory architectures
 
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Towards generic low-power area-efficient standard cell based memory architectures

Meinerzhagen, Pascal Andreas  
•
Roth, C.
•
Burg, Andreas Peter  
2010
2010 53rd IEEE International Midwest Symposium on Circuits and Systems
2010 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

Digital IC designers often use SRAM macrocells to implement on-chip memory functionality. In this paper we argue that in several situations, standard cell based memories (SCMs) can have advantages over SRAM macrocells. Various ways to implement SCMs are presented and compared to each other for different CMOS technologies and standard cell libraries and to corresponding macrocells, aiming for finding the most adequate memory option for each application. The benefits and drawbacks of SCMs compared to macrocells are illustrated with the example of a low-power low-density parity check (LDPC) decoder.

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PID1319151.pdf

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