This work reports the results of a layout-aware substrate modeling methodology for HVCMOS technologies. The model relies on the extraction of parasitic substrate network to simulate with circuit software parasitic lateral NPN bipolar transistors with multi-collector configuration. This allows to predict and analyze the injected substrate currents distribution through the chip and to explore different layout strategies to reduce the propagation of minority carriers through the substrate. Simulations results show good agreement in comparison with measurements at different temperatures.