conference paper not in proceedings
Design Space of Twin Gate Junctionless Vertical Slit Field Effect Transistors
2013
In this work, we present the technological constrains and limitations in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space involving the intrinsic off-current, the sub-threshold swing, and the drain induced barrier lowering is investigated with respect to the technological parameters. This work could serve as a guideline for technology optimization and design of JL VeSFETs.
Type
conference paper not in proceedings
Date Issued
2013
Subjects
Editorial or Peer reviewed
REVIEWED
Written at
EPFL
| Event name | Event place | Event date |
Gdynia, Poland | June 20-22, 2013 | |
Available on Infoscience
August 7, 2013
Use this identifier to reference this record