Three-dimensional (3D) imaging has become an increasingly important research field, with applications spanning the automotive industry, consumer electronics, bioimaging, virtual and augmented reality, and space instrumentation. Real-time, high-frame-rate imaging in such demanding environments requires the acquisition of large data volumes at high readout speeds, while simultaneously maintaining low noise levels to ensure high-quality depth reconstruction.

Direct time-of-flight (dToF) imaging has emerged as a compelling candidate for these applications. By combining light detection and ranging (LiDAR) techniques with low-noise, high-sensitivity photodetectorsâ such as single-photon avalanche diodes (SPADs)â and accurate timing circuits, including time-to-digital converters (TDCs) and time-gating architectures supported by phase-locked loops (PLLs), sub-nanosecond timing precision can be achieved. This level of precision enables millimeter-scale depth resolution, even under challenging operating conditions.

This thesis focuses on improving the frame rate of SPAD-based dToF integrated circuits (ICs). Although LiDAR is used as the primary application example, the concepts and methods presented here are broadly applicable to other imaging domains, provided that the pixel front-end is adapted accordingly. The work begins with the characterization of a 45~nm/22~nm 3D-stacked SPAD imager featuring on-chip data processing. Both architectural and device-level measurements were performed, and the insights gained from this characterization informed the subsequent IC developments.

Leveraging this experience, three additional CMOS SPAD imagers were designed. Each implementation explores different architectural strategies aimed at improving frame rate and signal-to-noise ratio (SNR). One line of work focuses on scalable and uniform coincidence detection to ensure consistent performance across the array. Another introduces event-driven readout, allowing the system to transmit data only when changes occur in the scene, thereby reducing bandwidth and improving temporal efficiency. Nearly all functional blocks were designed to be programmable, enabling proof-of-concept evaluation across a wide range of operating conditions, including long-range and low-light scenarios.

In summary, this thesis introduces several new techniques for on-chip data processing in SPAD imagers, including a novel coincidence architecture and a dual-threshold digital event-based processing scheme. It is anticipated that the contributions of this work will support future advances in high-speed 3D imaging and enable further scientific and technological developments in the field.\