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  4. A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18µm digital CMOS technology
 
conference paper

A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18µm digital CMOS technology

Tajalli, Armin  
•
Muller, Paul  
•
Atarodi, Mojtaba
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2005
Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC)
31st European Solid-State Circuits Conference ESSCIRC

This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying the required specifications for short-haul receivers. Implemented in a 0.18µm digital CMOS technology, total power dissipation is 70.2mW or 3.51mW/Gbps/Ch and each channel occupies 0.045µm2 silicon area.

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05_ESSCIRC_CDR_Tajalli.pdf

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