This paper investigates the radiation tolerance of 28-nm bulk n and pMOSFETs up to 1 Grad of total ionizing dose (TID). The radiation effects on this commercial 28-nm bulk CMOS process demonstrate a strong geometry dependence as a result of the complex interplay of oxide and interface charge trapping relevant to the gate-related dielectrics and the shallow trench isolation. The narrowest/longest channel devices have the most serious performance degradation. In addition, nMOSFETs present a limited on-current variation and a significant off-current increase, while pMOSFETs show a negligible off-current change and a substantial on-current degradation. The postirradiation annealing annihilates or neutralizes oxide trapped positive charges and tends to partly recover the degraded device performance. To quantify the effects of TID and postirradiation annealing, parameters including the threshold voltage, the free carrier mobility, the subthreshold swing, and the drain-induced barrier lowering are extracted.