A time-to-digital converter (TDC) architecture is presented enabling a time resolution of 17 ps over 50 ns and achieving twenty million conversions per second. The TDC, designed in a 65nm FPGA, is implemented as a pipelined interpolating architecture; it comprises a coarse time discriminator and a fine delay line, capable of sustained operation at a clock frequency of 300 MHz. An alternative version of the TDC implements an architecture with suppressed dead time to reach a conversion rate of 300 MS/s at the expense of a systematic asymmetry that requires fast error correction. Process, voltage, and temperature (PVT) variations are compensated in part via a calibration technique embedded in the TDC implementation. Results demonstrate the suitability of the approach for a variety of applications involving high-precision ultra-fast time discrimination, such as optical lifetime sensing, time-of-flight cameras, high throughput comlinks, RADARs, etc.