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conference paper
Characterization & Modeling of Gate-Induced-Drain-Leakage with complete overlap and fringing model
2010
Proceedings of the 23rd IEEE International Conference on Microelectronic Test Structures (ICMTS)
This paper investigates and models Gate Induced Drain Leakage (GIDL) for a wide variety of high voltage devices with different low doped drain (LDD) structures. Based on TCAD simulations, we propose semi-analytical a pseudo-2D model for Gate induced Drain leakage. This model includes a complete modeling of the overlap region accounting for technological process and bulk bias dependency through detailed electric field description.
Type
conference paper
Authors
Rideau, D.
•
Quenette, V.
•
•
Dornel, E.
•
Weybright, M.
•
Manceau, J. P.
•
Saxod, O.
•
Tavernier, C.
•
Jaouen, H.
Publication date
2010
Publisher
Published in
Proceedings of the 23rd IEEE International Conference on Microelectronic Test Structures (ICMTS)
Publisher place
Piscataway, NJ, USA
Start page
210
End page
213
Peer reviewed
NON-REVIEWED
EPFL units
| Event name | Event place | Event date |
Hiroshima, Japan | March 22-25, 2010 | |
Available on Infoscience
October 31, 2011
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