In this paper a design-oriented model for asymmetrical double-gate (ADG) MOSFETs is proposed. Including the back-gate effect into the original simplified EKV bulk model requires only one additional parameter to the existing four, and extends the simplified EKV model to FDSOI processes. This will help the designer to find the right trade-off in terms of design parameters, including the back-gate biasing. A comparison with measurement results from a 28-nm FDSOI CMOS process is provided, assessing the excellent accuracy of the proposed.