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  4. GENES IV: A Bit-Serial Processing Element for a Multi-Model Neural-Network Accelerator
 
research article

GENES IV: A Bit-Serial Processing Element for a Multi-Model Neural-Network Accelerator

Ienne, Paolo  
•
Viredaz, Marc A.
1995
Journal of VLSI Signal Processing
  • Details
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Type
research article
DOI
10.1007/BF02407088
Web of Science ID

WOS:A1995RC90800008

Author(s)
Ienne, Paolo  
Viredaz, Marc A.
Date Issued

1995

Published in
Journal of VLSI Signal Processing
Volume

9

Issue

3

Start page

257

End page

273

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LAP  
Available on Infoscience
August 8, 2005
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/215160
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