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conference paper

Physical Design Issues in 3-D Integrated Technologies

Pavlidis, Vasilis F.
•
Friedman, Eby G.
2010
VLSI-SOC: Design Methodologies for SoC and SiP
16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC 2008)

Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for 2-D circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits, while considering different forms of vertical integration, such as systems-in-package and 3-D ICs with fine grain vertical interconnections. The techniques described in this chapter address important physical design issues and fundamental interconnect structures in the 3-D design process.

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Type
conference paper
DOI
10.1007/978-3-642-12267-5_1
Web of Science ID

WOS:000303265900001

Author(s)
Pavlidis, Vasilis F.
Friedman, Eby G.
Date Issued

2010

Publisher

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa

Published in
VLSI-SOC: Design Methodologies for SoC and SiP
Series title/Series vol.

IFIP Advances in Information and Communication Technology; 313

Start page

1

End page

21

Subjects

Clock Distribution Networks

•

On-Chip

•

Circuits

•

Ics

•

Placement

•

Performance

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LSI1  
Event nameEvent placeEvent date
16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC 2008)

Rhodes, Greece

Oct 13-15, 2008

Available on Infoscience
June 25, 2012
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/82368
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