A 300Hz 19b DR capacitive accelerometer based on a versatile front end in a 5th-order ΔΣ loop
This paper presents a 5th-order ΔΣ capacitive accelerometer. The ΔΣ loop is implemented in mixed signal, the global 5th-order filter having a 2nd-order analog and a 3rd-order digital part. The system can be used with a wide range of sensors, because the mixed-signal front end is programmable. The ASIC developed comprises a voltage-mode preamplifier, two parallel demodulators implementing CDS, and a 7-bit Flash ADC. The latter drives a 3rd-order digital filter, which can be configured for different sensor parameters in order to ensure overall loop stability and optimize the noise performance. With a low-noise MEMS sensor, the system achieves a 19-bit DR and a 16-bit SNR, both over a 300Hz bandwidth.
WOS:000276195800064
2-s2.0-72849131449
2009
978-1-4244-4355-0
Proceedings of the European Solid-State Circuits Conference
289
292
STI IEL ELab., EPFL, Lausanne, Switzerland IME, FHNW, Windisch, Switzerland Colibrys SA, Neuchâtel, Switzerland
Export Date: 19 January 2010
Source: Scopus
Art. No.: 5326033
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EPFL
| Event name | Event place | Event date |
Athens, GREECE | Sep 14-18, 2009 | |