In this paper we study a particular class of generalized Reed-Solomon codes and introduce encoding and decoding algorithms for such codes that speed up current hardware implementations by a factor p wherein p can be any divisor of the size of the multiplicative group of the underlying field. In many cases, p can be chosen to be 3, for example. In some cases, for example when the size of the base field is 256, the speed-up factor can be as large as 15 at the expense of very little increase in the hardware area.