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  4. A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI
 
research article

A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI

Giterman, R
•
Fish, A
•
Burg, A
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2018
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
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Type
research article
DOI
10.1109/TCSI.2017.2747087
Web of Science ID

WOS:000427578800008

Author(s)
Giterman, R
Fish, A
Burg, A
Teman, A
Date Issued

2018

Published in
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume

65

Issue

4

Start page

1245

End page

1256

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
TCL  
Available on Infoscience
November 8, 2018
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/149724
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