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conference paper

Ultra Low Power Subthreshold MOS Current Mode Logic Circuits Using a Novel Load Device Concept

Tajalli, Armin  
•
Leblebici, Yusuf  
•
Vittoz, Eric  
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2007
Proceedings of the 33rd European Solid-State Circuits Conference (ESSCIRC)
33rd European Solid-State Circuits Conference (ESSCIRC)

This article presents a novel and robust approach for implementing ultra-low power MOS current mode logic (MCML) circuits. To operate at very low bias currents, a simple and compact high resistance load device has been introduced. Operating in subthreshold regime, the circuit can be used in a very wide frequency range by adjusting the bias current without any need for resizing the devices. Measurements in 0.18 μm CMOS technology show that the proposed MCML circuit can be operated reliably with bias currents as low as 1 nA offering a significant improvement of the power-delay product compared to conventional CMOS gates. Simulations show that the proposed circuit exhibits faster response compared to the conventional MCML circuits with triode-mode PMOS load devices at low bias currents.

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Type
conference paper
DOI
10.1109/ESSCIRC.2007.4430304
Web of Science ID

WOS:000252830900065

Author(s)
Tajalli, Armin  
•
Leblebici, Yusuf  
•
Vittoz, Eric  
•
Brauer, Elizabeth J.
Date Issued

2007

Published in
Proceedings of the 33rd European Solid-State Circuits Conference (ESSCIRC)
Subjects

CMOS digital integrated circuits

•

Source-coupled logic

•

Ultra low power circuits

Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
LSM  
Event nameEvent placeEvent date
33rd European Solid-State Circuits Conference (ESSCIRC)

Munich, Germany

September 11-13

Available on Infoscience
June 21, 2007
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/9175
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