conference paper
A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering
2000
2000 IEEE International Symposium on Circuits and Systems (ISCAS)
Type
conference paper
Author(s)
Hatirnaz, I.
Date Issued
2000
Published in
2000 IEEE International Symposium on Circuits and Systems (ISCAS)
Volume
4
Start page
685
End page
688
Written at
EPFL
EPFL units
| Event name | Event place | Event date |
Geneva, Switzerland | May 2000 | |
Available on Infoscience
August 30, 2005
Use this identifier to reference this record