Repository logo

Infoscience

  • English
  • French
Log In
Logo EPFL, École polytechnique fédérale de Lausanne

Infoscience

  • English
  • French
Log In
  1. Home
  2. Academic and Research Output
  3. Conferences, Workshops, Symposiums, and Seminars
  4. FPGA-to-CPU Undervolting Attacks
 
conference paper

FPGA-to-CPU Undervolting Attacks

Mahmoud, Dina Gamaleldin Ahmed Shawky  
•
Hussein, Samah
•
Lenders, Vincent
Show more
March 22, 2022
Proceedings Of The 2022 Design, Automation & Test In Europe Conference & Exhibition
25th Design, Automation and Test in Europe

FPGAs are proving useful and attractive for many applications, thanks to their hardware reconfigurability, low power, and high-degree of parallelism. As a result, modern embedded systems are often based on systems-on-chip (SoCs), where CPUs and FPGAs share the same die. In this paper, we demonstrate the first undervolting attack in which the FPGA acts as an aggressor while the CPU, residing on the same SoC, is the victim. We show that an adversary can use the FPGA fabric to create a significant supply voltage drop which, in turn, faults the software computation performed by the CPU. Additionally, we show that an attacker can, with an even higher success rate, execute a denial-of-service attack, without any modification of the underlying hardware or the power distribution network. Our work exposes a new electrical-level attack surface, created by tight integration of CPUs and FPGAs in m

  • Files
  • Details
  • Metrics
Type
conference paper
DOI
10.23919/DATE54114.2022.9774663
Web of Science ID

WOS:000819484300185

Author(s)
Mahmoud, Dina Gamaleldin Ahmed Shawky  
Hussein, Samah
Lenders, Vincent
Stojilovic, Mirjana  
Date Issued

2022-03-22

Publisher

IEEE

Published in
Proceedings Of The 2022 Design, Automation & Test In Europe Conference & Exhibition
ISBN of the book

978-3-9819263-6-1

Total of pages

6

Start page

999

End page

1004

Subjects

FPGA

•

CPU

•

Security

•

Undervolting

•

Fault injection

Note

This research is supported by armasuisse Science and Technology.

Editorial or Peer reviewed

REVIEWED

Written at

EPFL

EPFL units
PARSA  
Event nameEvent placeEvent date
25th Design, Automation and Test in Europe

Antwerp, Belgium [Virtual]

March 14-23, 2022

Available on Infoscience
January 24, 2022
Use this identifier to reference this record
https://infoscience.epfl.ch/handle/20.500.14299/184727
Logo EPFL, École polytechnique fédérale de Lausanne
  • Contact
  • infoscience@epfl.ch

  • Follow us on Facebook
  • Follow us on Instagram
  • Follow us on LinkedIn
  • Follow us on X
  • Follow us on Youtube
AccessibilityLegal noticePrivacy policyCookie settingsEnd User AgreementGet helpFeedback

Infoscience is a service managed and provided by the Library and IT Services of EPFL. © EPFL, tous droits réservés